1. Field of the Invention
The present invention relates to a method of forming a pattern for a semiconductor device. More particularly, the present invention relates to a method of forming a fine pitch pattern having a feature width under several tens of nanometers for a semiconductor device using sacrificial layer patterns.
2. Description of the Related Art
As semiconductor devices become increasingly integrated for economic efficiency, the design rule of the devices becomes smaller. Therefore, the topological dimensions for a pattern for the semiconductor devices decrease, and the minimum line width is reduced to a range of several hundreds to several tens of nanometers. Recently, pattern miniaturization and integration of semiconductor devices has been highly dependent upon developments in photolithography. That is, due to the resolution limit obtainable with the equipment and materials used thus far in the photolithography process, the amount of pattern miniaturization and integration possible in semiconductor devices has been limited.
Several problems associated with a conventional method of forming patterns for semiconductor devices are disclosed hereinafter.
As shown in FIG. 1A, a base layer 12 acting as an interlayer insulation film 12 is formed on a semiconductor substrate 10. A layer 13, to be a predetermined pattern, is formed on the base layer 12, and subsequently a photoresist film (not shown) is formed on the layer 13. Then, as shown in FIG. 1B, a photoresist film pattern 16 is formed by exposing and developing the photoresist film. Next, as shown in FIG. 1C, the layer 13 is partially etched to expose the base layer 12 using the photoresist film pattern 16 as an etching mask, so that predetermined pattern layers 13a, 13b, such as metal wires or gate electrodes, are formed.
Ordinarily, fine pitch patterns are formed in a memory cell region while large pitch patterns are formed in a peripheral region relative to the memory cell region. Therefore, the resolution capability of a photoresist film must be enhanced in order to form the fine pitch patterns. This resolution requirement defines the need for a feature of the present invention.
The resolution capability of a photoresist film is usually improved by employing a light source having a short wavelength, or by incrementing a numerical aperture (NA) of a lens. With respect to the light source, a DUV (deep ultraviolet) light source such as KrF (248 nm) or ArF (193 nm) having a wavelength shorter than G-line (436 nm) or I-line (365 nm) has been used, and an X-ray light source is being developed.
Moreover, there have been other attempts to form the fine pitch patterns for semiconductor devices, such as modifying a mask pattern into a phase shift mask (PSM) to prevent imprecise pattern formation due to an optical proximity effect, or employing an off axis illumination method.
However, the various approaches described above for forming fine pitch patterns in a memory cell, photolithography using a DUV or X-ray light source, modifying a mask pattern into PSM, and employing an off axis illumination method, require costly manufacturing equipment and a process that is more precisely controlled and complicated than that of conventional photolithography techniques. For instance, using a DUV or an X-ray as a light source requires new photoresist materials that are sensitive to the short wavelength of the DUV or the X-ray. Moreover, using the X-ray as a light source requires development of a new opaque material to obstruct transmission of the X-ray used in an X-ray photolithography process.
As a result, expensive equipment and complicated process conditions are necessary to form fine pitch patterns by means of the photolithography process, thereby increasing the manufacturing costs for a semiconductor device while decreasing the productivity thereof.
In addition, up until now, highly integrated semiconductor devices having miniaturized patterns have not been attainable with a conventional photolithography process, hence the alternate, more costly approaches described above.
It is, therefore, a feature of an embodiment of the present invention to provide a method for forming a pattern of a semiconductor device using sacrificial layer patterns.
It is another feature of an embodiment of the present invention to provide a method of forming a pattern for semiconductor devices using the conventional photolithography process, wherein the pattern preferably has a line width under several tens of nanometers.
It is yet another feature of an embodiment of the present invention to provide a method of forming patterns for a semiconductor device, comprising forming a first pattern, preferably of minimum line width under several tens of nanometers, and a second pattern having a line width relatively greater than that of the first pattern by combining a photolithography process and a non-photolithography process.
In order to provide the above features of the present invention, according to an embodiment of the present invention, there is provided a method of forming a pattern for a semiconductor device comprising forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the sacrificial layer, forming a conformal layer on a resultant structure after forming the sacrificial layer pattern, and forming a layer pattern by anisotropically etching the conformal layer.
In addition, a base layer may be formed between the semiconductor substrate and the sacrificial layer.
In a method according to an embodiment of the present invention, the sacrificial layer is formed from a material having a high etching selectivity to the conformal layer and the semiconductor substrate, wherein the sacrificial layer is preferably formed of silicon nitride.
In the method according to an embodiment of the present invention, the conformal layer is preferably a conductive layer formed of a material from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon. Further, the conformal layer may be a polycide double layer including a polysilicon layer and a silicide layer, or a multilayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
In the method according to an embodiment of the present invention, the method further includes planarizing an upper surface of the sacrificial layer pattern and the layer pattern after forming the layer pattern.
In the method according to an embodiment of the present invention, the method further includes removing the sacrificial layer pattern by means of a wet etching process after forming the layer pattern.
According to another embodiment of the present invention, there is provided a method of forming patterns for semiconductor devices comprising forming a sacrificial layer on a semiconductor substrate having a cell region and a peripheral region; forming a sacrificial layer pattern on the semiconductor substrate of the cell region; forming a conformal layer on the entire surface of the semiconductor substrate including the sacrificial layer pattern; forming a photoresist pattern on the conformal layer formed at the peripheral region; and anisotropically etching the conformal layer to expose the semiconductor substrate, thereby forming a first pattern comprised of the conformal layer on the sidewalls of the sacrificial layer pattern at the cell region, and forming a second pattern beneath the photoresist patterns at the peripheral region, wherein the second pattern has a width relatively wider than that of the first patterns.
In addition, a base layer may be formed between the semiconductor substrate and the sacrificial layer.
In the method according to an embodiment of the present invention, the sacrificial layer is preferably formed of a material having a high etching selectivity to the semiconductor substrate, the base layer and the conformal layer.
In the method according to an embodiment of the present invention, the sacrificial layer is preferably formed of silicon nitride.
In the method according to an embodiment of the present invention, the conformal layer is preferably a conductive layer.
In the method according to an embodiment of the present invention, the conformal layer is preferably selected from the group consisting of aluminum, tungsten, cobalt, copper, titanium and polysilicon. The conductive layer may also be formed of a double layer comprised of a polysilicon layer and a suicide layer, or a multiplayer, the multilayer being formed of films selected from the group consisting of a titanium film, an aluminum film, and a titanium nitride film.
In the method according to an embodiment of the present invention, the method further includes planarizing an upper surface of the sacrificial layer pattern and the first and second patterns after anisotropically etching the layer.
In the method according to an embodiment of the present invention, the method further includes removing the sacrificial layer pattern by means of a wet etching process after anisotropically etching the layer.
In the method according to an embodiment of the present invention, the sacrificial layer pattern is formed at the cell region and the peripheral region, respectively; during forming the sacrificial layer pattern, the photoresist film pattern is formed on the layer at the peripheral region, and while the second pattern is formed beneath the photoresist film pattern during anisotropic etching of the layer, a dummy pattern is formed on sidewalls of the sacrificial layer pattern at the peripheral region.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description of the preferred embodiments that follows.